1. Field of the Invention
The present invention relates to an image display apparatus and to a method for employing a display device to display an image. In particular, the present invention pertains to an arrangement for forming an image on a plane.
2. Related Background Art
FIG. 15 is a diagram illustrating a conventional image display apparatus that displays an image by employing pulse width modulation for which all start times for driving modulation signals are identical. FIG. 16 is a timing chart showing the operational timing for the image display apparatus. In FIG. 15, the image display apparatus comprises: a timing controller 1, for generating the operational timing for the apparatus; an A/D converter 2, for converting an image signal S1 into a digital signal S2 representing the luminance of each pixel; a display panel 4, across which display devices are distributed, one at each intersection of lines arranged as columns and rows; a column selection controller 3, for controlling the selection of the lines arranged as columns on the display panel 4; a shift register 5, for distributing the digital image signal S2; PWM generators 6, for performing pulse width modulation for a luminance signal received by the shift register 5 and for controlling the display luminance; and a row driver 7, which includes the shift register 5 and the PWM generators 6.
With this arrangement, an input image signal S1 is converted by the A/D converter 2 into a digital signal S2 representing the luminance of each pixel, and the digital signal is transmitted to the PWM generator 6 for a pixel. Each of the PWM generators 6 employs a signal from the timing controller 1 to modulate the luminance signal to obtain a pulse length, and drives a line arranged as a row on the display panel 4. At the same time, the column selection controller 3 sequentially drives a column corresponding to a pixel that is to be displayed. Individual devices can therefore be driven in accordance with the image signals.
The structure of a PWM generator 6 is shown in FIG. 17, and the operational timing is shown in FIG. 19. In FIG. 17, a clock generator 10 supplies a clock pulse S10. Upon the arrival of the clock pulse at a terminal CK, a down counter 11 decrements by one the value held by an internal register ct (not shown). When the counter value reaches 0, the counting by the down counter 11 is halted and a terminal NZ is set high. Then, when a pulse is input at a terminal LOAD, the down counter 11 loads an input value DATA into the internal register, and resumes the counting. And an output driver 12 receives the level set for the terminal NZ of the down counter 11 and drives the display panel 4.
A signal S11 received at the terminal LOAD of the down counter 1 is a timing signal for loading the luminance signal S12, and is either a horizontal synchronization signal or another signal based on it. The luminance signal S12 input at the terminal DATA is a digital luminance signal; a signal S13 (FIG. 19) is a value held in the register ct of the down counter 11; a signal S14 goes high when the internal register value S13 is other than 0; and a signal S15 emitted by the output driver 12 is a modulation signal output in accordance with the signal S14.
In FIG. 15, the thus arranged PWM generator 6 performs the above operation to modulate into a pulse length the luminance signal received from the shift register 5, and outputs the resultant signal to the display panel 4.
In the arrangement in FIG. 15, for example, a floating capacitance called an inter-line capacitance is present between the individual lines of the display panel 4. If a drive signal having a waveform shown in FIG. 20 is to be transmitted to the n-th line, for example, the signal for the n-th line is affected by the trailing edges of drive signals that are transmitted to the adjacent (n−1)th and (n+1)th lines, and its waveform is distorted as is shown in FIG. 21. This occurs because of crosstalk induced by inter-line capacitance.